Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and examples of volatile memory include random-access memory (RAM), dynamic random-access memory (DRAM), and synchronous dynamic random-access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and examples of non-volatile memory include flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory, such as phase-change random-access memory (PCRAM), resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), and three-dimensional (3D) XPoint™ memory, among others.
Flash memory is utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of one-transistor, floating gate or charge trap memory cells that allow for high memory densities, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named after the logic form in which the basic memory cell configuration of each is arranged. The memory cells of the memory array are typically arranged in a matrix. In an example, the gates of each floating gate memory cell in a row of the array are coupled to an access line (e.g., a word line). In a NOR architecture, the drains of each memory cell in a column of the array are coupled to a data line (e.g., a bit line). In a NAND architecture, the memory cells in a string of the array are coupled together in series, source to drain, between a source line and a bit line.
Both NOR and NAND architecture semiconductor memory arrays are accessed through decoders that activate specific memory cells by selecting the word line coupled to their gates. In a NOR architecture semiconductor memory array, once activated, the selected memory cells place their data values on bit lines, causing different currents to flow depending on the state at which a particular cell is programmed In a NAND architecture semiconductor memory array, a high bias voltage is applied to a drain-side select gate (SGD) line. Word lines coupled to the gates of the unselected memory cells of each group are driven at a specified pass voltage (e.g., Vpass) to operate the unselected memory cells of each group as pass transistors (e.g., to pass current in a manner that is unrestricted by their stored data values). Current then flows from the source line to the bit line through each series coupled group, restricted only by the selected memory cells of each group, placing current encoded data values of selected memory cells on the bit lines.
Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or a number of programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), representing one bit of data. However, flash memory cells can also represent one of more than two programmed states, allowing the manufacture of higher density memories without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit). Such cells can be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In certain examples, MLC can refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), a triple-level cell (TLC) can refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and a quad-level cell (QLC) can store four bits of data per cell. MLC is used herein in its broader context, to can refer to any memory cell that can store more than one bit of data per cell (i.e., that can represent more than two programmed states).
Traditional memory arrays are two-dimensional (2D) structures arranged on a surface of a semiconductor substrate and can be referred to as a planar memory array. To increase memory capacity for a given area, and to decrease cost, the size of the individual memory cells has decreased. However, there is a technological limit to the reduction in size of the individual memory cells, and thus, to the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as 3D NAND architecture semiconductor memory devices, are being developed to further increase memory density and lower memory cost.
Such 3D NAND devices often include strings of storage cells, coupled in series (e.g., drain to source), between one or more source-side select gates (SGSs) proximate a source, and one or more drain-side select gates (SGDs) proximate a bit line. In an example, the SGSs or the SGDs can include one or more field-effect transistors (FETs) or metal-oxide semiconductor (MOS) structure devices, etc. In some examples, the strings will extend vertically, through multiple vertically spaced tiers containing respective word lines. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent a string of storage cells to form a channel for the storages cells of the string. In the example of a vertical string, the polysilicon structure may be in the form of a vertically extending pillar. In some examples, the string may be “folded,” and thus arranged relative to a U-shaped pillar. In other examples, multiple vertical structures may be stacked upon one another to form stacked arrays of storage cell strings.
Memory arrays or devices can be combined together to form a storage volume of a memory system, such as a solid-state drive (SSD), a Universal Flash Storage (UFS™) device, a MultiMediaCard (MMC) solid-state storage device, an embedded MMC device (eMMC™), etc. An SSD can be used as, among other things, the main storage device of a computer, having advantages over traditional hard drives with moving parts with respect to, for example, performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, SSDs can have reduced seek time, latency, or other delay associated with magnetic disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells, such as flash memory cells to obviate internal battery supply requirements, thus allowing the drive to be more versatile and compact.
An SSD can include a number of memory devices, including a number of dies or logical units (e.g., logical unit numbers or LUNs), and can include one or more processors or other controllers performing logic functions required to operate the memory devices or interface with external systems. Such SSDs may include one or more flash memory die, including a number of memory arrays and peripheral circuitry thereon. The flash memory arrays can include a number of blocks of memory cells organized into a number of physical pages. In many examples, the SSDs will also include DRAM or SRAM (or other forms of memory die or other memory structures). The SSD can receive commands from a host in association with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, or erase operations to erase data from the memory devices.
In NAND flash based storage systems, data stored in a NAND memory device can be categorized with respect to how frequently data is overwritten, that is, how frequently data is written to an address by a host processor or processors, where a logical block address (LBA) can be provided as the address. One or more host processors may be referred to herein as a host or host processor. Host data typically consists of different flavors of data, where data at an LBA can be categorized in terms of a data temperature. Data temperature is a measure of frequency of access. Cold data is data at an address that is not frequently over-written by a host. Cold data may be considered as static data such as media files which are not often rewritten, examples of which can include, but is not limited to, an operating system (OS), video files, music files, and pictures. Hot data is data at an address that is frequently over-written by a host. Hot data, which effectively may be continuously being over-written by a host, can include, for example but not limited to, system metadata. Metadata is data that is information about other data. The data temperatures can also include other temperatures such as normal, warm, and other graduations of frequency of access fro rewriting. In workloads for SSD and mobile device applications, a host does not specify which data is hot and which data is cold when sending a write command to a memory device.
To maintain continuous pool of free blocks for host data, firmware continuously does garbage collection (GC) at the system level. Firmware for a device can comprise instructions, such as microcode, which when executed by a controller such as a processor, can cause the device to perform operations. A GC procedure for a NAND device structure is directed to recover free space when the free physical space in the NAND device becomes low. GC typically includes recopying logical valid pages from a source block to a destination block. However, GC can be a factor that causes write amplification. Write amplification is a condition associated with flash memories and solid-state drives in which the actual amount of information physically written to the storage media is a multiple of the logical amount intended to be written.
Since flash memory is erased before it can be rewritten, the process to perform these operations results in rewriting, realized by moving, host data and metadata more than once. The erase operation is associated with coarser granularity compared to the write operation. As a result, larger portions of flash are erased and rewritten than actually required by the amount of new data from the host. This multiplying effect increases the number of writes required over the life of the SSD which shortens the time it can reliably operate. A write amplification factor can be calculated as is a numerical value that represents the amount of data a solid state storage controller has to write in relation to the amount of data that the host's flash controller has to write. The numerical value can be calculated as a rate by dividing the amount of data written to the flash memory by the amount of data written by the host. A write amplification factor of one means that the amount of data written to a flash memory equals the amount of data written by the host. Many elements contribute to the write amplication factor including efficiency of the GC procedure. Garbage collection eats away into the bandwidth of a memory controller, because the controller now has to service both host as well garbage collection events. Enhancements to memory structure and processes to minimize or reduce garbage collection can allow a memory controller to increase its maximum time servicing the host. In NAND flash based storage systems, improvements of NAND flash based storage systems can include improvements in garbage collection in the arrangement of data storage within a NAND memory device.